Nand2Tetris — Capítulo 3

//Registro de 1 bit [citar: 2]
//Entrada: entrada, carga (1 bit) [citar: 3]
//Salida: salida (1 bit) [citar: 4]
//Acción: Si la carga es 1 (afirmada), el valor del registro se establece en [citar: 2].
//De lo contrario, el registro conserva su valor actual (si load(t) out(t+1) = in(t), de lo contrario out(t+1) = out(t))[citar: 3].

CHIP Bit {
    IN in, load;
    OUT out;

    PARTS:
    Mux(a=DFFO , b=in , sel=load , out=MuxO );
    DFF(in=MuxO , out=DFFO, out=out );
}

//Contador de programa de 16 bits
//entrada: en [16], cargar, inc, restablecer [citar: 5]
//salida: salida[16] [citar: 5]
//Operación: Determina el valor del registro para el siguiente ciclo de reloj de acuerdo con las prioridades de las señales de reinicio, carga e inc [citar: 6].

CHIP PC {
    IN in[16], load, inc, reset;
    OUT out[16];

    PARTS:
    Inc16(in=regOut, out=incOut);
    Mux16(a=regOut, b=incOut, sel=inc, out=mux1);

    Mux16(a=mux1, b=in, sel=load, out=mux2);

    Mux16(a=mux2, b=false, sel=reset, out=mux3);

    Register(in=mux3, load=true, out=regOut, out=out);
}

//Registro de 16 bits [citar: 34]
//entrada: en [16], carga [citar: 35]
//salida: fuera[16] [citar: 36]
//Acción: Si la carga es 1 (afirmada), el valor del registro se establece en [citar: 34].
//De lo contrario, mantenga el valor actual [cita: 35]. Chips de 16 bits conectados en paralelo [citar: 36, 37, 38, 39, 40, 41].

CHIP Register {
    IN in[16], load;
    OUT out[16];

    PARTS:
    Bit(in=in[0] , load=load , out=out[0] );
    Bit(in=in[1] , load=load , out=out[1] );
    Bit(in=in[2] , load=load , out=out[2] );
    Bit(in=in[3] , load=load , out=out[3] );
    Bit(in=in[4] , load=load , out=out[4] );
    Bit(in=in[5] , load=load , out=out[5] );
    Bit(in=in[6] , load=load , out=out[6] );
    Bit(in=in[7] , load=load , out=out[7] );
    Bit(in=in[8] , load=load , out=out[8] );
    Bit(in=in[9] , load=load , out=out[9] );
    Bit(in=in[10] , load=load , out=out[10] );
    Bit(in=in[11] , load=load , out=out[11] );
    Bit(in=in[12] , load=load , out=out[12] );
    Bit(in=in[13] , load=load , out=out[13] );
    Bit(in=in[14] , load=load , out=out[14] );
    Bit(in=in[15] , load=load , out=out[15] );
}

//Memoria de ocho registros de 16 bits [citar: 12]
//entrada: en [16], carga, dirección [3] [cita: 15]
//salida: fuera[16] [citar: 15]
//Acción: Si la carga es 1, el valor del registro seleccionado por dirección se establece en [citar: 13].
//De lo contrario, el valor no se cambia y el valor del registro seleccionado se emite [citar: 14].

CHIP RAM8 {
    IN in[16], load, address[3];
    OUT out[16];
    PARTS:
    DMux8Way(in=load, sel= address,
    a= Out0, b= Out1,
    c= Out2, d= Out3,
    e= Out4, f= Out5,
    g= Out6, h= Out7);
    Register(in=in , load=Out0 , out=R0 );
    Register(in=in , load=Out1 , out=R1 );
    Register(in=in , load=Out2 , out=R2 );
    Register(in=in , load=Out3 , out=R3 );
    Register(in=in , load=Out4 , out=R4 );
    Register(in=in , load=Out5 , out=R5 );
    Register(in=in , load=Out6 , out=R6 );
    Register(in=in , load=Out7 , out=R7 );
    Mux8Way16(
    a= R0, b= R1,
    c= R2, d= R3,
    e= R4, f= R5,
    g= R6, h= R7,
    sel= address, out=out);
}

//memoria de 64 palabras
//entrada: en [16], carga, dirección [6] [cita: 25]
//salida: fuera[16] [citar: 25]
//Operación: Combinando 8 chips RAM8 para formar 64 registros [citar: 26, 27, 28].

CHIP RAM64 {
    IN in[16], load, address[6];
    OUT out[16];
    PARTS:
    DMux8Way(in=load, sel=address[3..5], a=loadA, b=loadB, c=loadC, d=loadD, e=loadE, f=loadF, g=loadG, h=loadH);

    RAM8(in=in, load=loadA, address=address[0..2], out=outA);
    RAM8(in=in, load=loadB, address=address[0..2], out=outB);
    RAM8(in=in, load=loadC, address=address[0..2], out=outC);
    RAM8(in=in, load=loadD, address=address[0..2], out=outD);
    RAM8(in=in, load=loadE, address=address[0..2], out=outE);
    RAM8(in=in, load=loadF, address=address[0..2], out=outF);
    RAM8(in=in, load=loadG, address=address[0..2], out=outG);
    RAM8(in=in, load=loadH, address=address[0..2], out=outH);

    Mux8Way16(a=outA, b=outB, c=outC, d=outD, e=outE, f=outF, g=outG, h=outH, sel=address[3..5], out=out);
}

//memoria de 512 palabras
//entrada: en [16], carga, dirección [9] [cita: 29]
//salida: fuera[16] [citar: 29]
//Operación: se combinan 8 chips RAM64 para formar 512 registros [citar: 30, 31, 32].

CHIP RAM512 {
    IN in[16], load, address[9];
    OUT out[16];
    PARTS:
    DMux8Way(in=load, sel=address[6..8], a=loadA, b=loadB, c=loadC, d=loadD, e=loadE, f=loadF, g=loadG, h=loadH);

    RAM64(in=in, load=loadA, address=address[0..5], out=outA);
    RAM64(in=in, load=loadB, address=address[0..5], out=outB);
    RAM64(in=in, load=loadC, address=address[0..5], out=outC);
    RAM64(in=in, load=loadD, address=address[0..5], out=outD);
    RAM64(in=in, load=loadE, address=address[0..5], out=outE);
    RAM64(in=in, load=loadF, address=address[0..5], out=outF);
    RAM64(in=in, load=loadG, address=address[0..5], out=outG);
    RAM64(in=in, load=loadH, address=address[0..5], out=outH);

    Mux8Way16(a=outA, b=outB, c=outC, d=outD, e=outE, f=outF, g=outG, h=outH, sel=address[6..8], out=out);
}

//Memoria de palabras 4K
//entrada: en [16], carga, dirección [12] [cita: 7]
//salida: salida[16] [citar: 7]
//Operación: se combinan 8 chips RAM512 para formar 4096 registros [citar: 8, 9, 10].

CHIP RAM4K {
    IN in[16], load, address[12];
    OUT out[16];
    PARTS:
    DMux8Way(in=load, sel=address[9..11], a=loadA, b=loadB, c=loadC, d=loadD, e=loadE, f=loadF, g=loadG, h=loadH);

    RAM512(in=in, load=loadA, address=address[0..8], out=outA);
    RAM512(in=in, load=loadB, address=address[0..8], out=outB);
    RAM512(in=in, load=loadC, address=address[0..8], out=outC);
    RAM512(in=in, load=loadD, address=address[0..8], out=outD);
    RAM512(in=in, load=loadE, address=address[0..8], out=outE);
    RAM512(in=in, load=loadF, address=address[0..8], out=outF);
    RAM512(in=in, load=loadG, address=address[0..8], out=outG);
    RAM512(in=in, load=loadH, address=address[0..8], out=outH);

    Mux8Way16(a=outA, b=outB, c=outC, d=outD, e=outE, f=outF, g=outG, h=outH, sel=address[9..11], out=out);
}

//Memoria de palabras de 16K
//entrada: en [16], carga, dirección [14] [cita: 22]
//salida: fuera[16] [citar: 22]
//Operación: Se combinan cuatro chips RAM4K con DMux4Way y Mux4Way16 para configurar 16384 registros [citar: 23, 24].

CHIP RAM16K {
    IN in[16], load, address[14];
    OUT out[16];
    PARTS:
    DMux4Way(in=load, sel=address[12..13], a=loadA, b=loadB, c=loadC, d=loadD);

    RAM4K(in=in, load=loadA, address=address[0..11], out=outA);
    RAM4K(in=in, load=loadB, address=address[0..11], out=outB);
    RAM4K(in=in, load=loadC, address=address[0..11], out=outC);
    RAM4K(in=in, load=loadD, address=address[0..11], out=outD);

    Mux4Way16(a=outA, b=outB, c=outC, d=outD, sel=address[12..13], out=out);
}